3955 search results - page 696 / 791 » A Transactional Architecture for Simulation |
198
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VLSID
2003
IEEE
2003
IEEE
Design of a 2D DCT/IDCT application specific VLIW processor supporting scaled and sub-sampled blocks
16 years 6 months ago
We present an innovative design of an accurate, 2D DCT IDCT processor, which handles scaled and sub-sampled input blocks efficiently. In the IDCT mode, the latency of the processo...
173
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MOBIHOC
2008
ACM
16 years 6 months ago
2008
ACM
Because of cost and resource constraints, sensor nodes do not have a complicated hardware architecture or operating system to protect program safety. Hence, the notorious buffer-o...
210
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MOBIHOC
2003
ACM
16 years 6 months ago
2003
ACM
The efficiency of a communication network depends not only on its control protocols, but also on its topology. We propose a distributed topology management algorithm that construc...
205
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SOSP
2009
ACM
16 years 3 months ago
2009
ACM
Modern computer systems have been built around the assumption that persistent storage is accessed via a slow, block-based interface. However, new byte-addressable, persistent memo...
194
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CSE
2009
IEEE
16 years 1 months ago
2009
IEEE
—In this paper we present a design methodology for the identification and development of a suitable hardware platform (including dedicated hardware accelerators) for the data pl...