3955 search results - page 547 / 791 » A Transactional Architecture for Simulation |
161
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EH
1999
IEEE
15 years 11 months ago
1999
IEEE
MorphoSys is a system-on-chip which combines a RISC processor with an array of reconfigurable cells. The important features of MorphoSys are coarse-grain granularity, dynamic reco...
178
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ICMCS
1999
IEEE
15 years 11 months ago
1999
IEEE
This paper presents design and architecture of the distributed virtual reality service (dvr) which allows collaboration-unaware VRML animations and simulations to be integrated in...
156
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IPPS
1999
IEEE
15 years 11 months ago
1999
IEEE
In this paper we propose a simple extension to the I/O architecture of scalable multiprocessors that optimizes page swap-outs significantly. More specifically, we propose the use o...
142
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ISCAS
1999
IEEE
15 years 11 months ago
1999
IEEE
A general high-Q biquad lter architecture capable of operating in the GHz range is proposed and analyzed. This lter, which is usable in bandpass and lowpass applications, utilizes...
151
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INFOCOM
1998
IEEE
15 years 11 months ago
1998
IEEE
Reliable sender-based one-to-many protocols do not scale well due mainly to implosion caused by excessive rate of feedback packets arriving from receivers. We show that this probl...