3955 search results - page 542 / 791 » A Transactional Architecture for Simulation |
255
Voted
FAABS
2004
Springer
16 years 2 days ago
2004
Springer
Abstract. The design of reactive systems must comply with logical correctness (the system does what it is supposed to do) and timeliness (the system has to satisfy a set of tempora...
179
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GCC
2004
Springer
16 years 2 days ago
2004
Springer
Trust establishment is hard in grid architecture by the ad hoc nature. To set up trust in large scale of network is more difficult. In this paper, we propose an automatic key manag...
178
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ICT
2004
Springer
16 years 1 days ago
2004
Springer
Abstract This paper presents a comparative evaluation of the Scalable ReservationBased QoS (SRBQ) and the RSVP Reservation Aggregation (RSVPRAgg) architectures, both designed to pr...
149
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APCSAC
2003
IEEE
15 years 12 months ago
2003
IEEE
The RAMpage hierarchy moves main memory up a level to replace the lowest-level cache by an equivalent-sized SRAM main memory, with a TLB caching page translations for that main mem...
141
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ASYNC
2003
IEEE
15 years 12 months ago
2003
IEEE
We present a high-speed, clockless, serial link transceiver for inter-chip communication in asynchronous VLSI systems. Serial link transceivers achieve high offchip data rates by ...