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» A Transactional Architecture for Simulation
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ISSS
2002
IEEE
125views Hardware» more  ISSS 2002»
15 years 11 months ago
Design Experience of a Chip Multiprocessor Merlot and Expectation to Functional Verification
We have fabricated a Chip Multiprocessor prototype code-named Merlot to proof our novel speculative multithreading architecture. On Merlot, multiple threads provide wider issue wi...
Satoshi Matsushita
180
Voted
ICS
2010
Tsinghua U.
15 years 11 months ago
Small-ruleset regular expression matching on GPGPUs: quantitative performance analysis and optimization
We explore the intersection between an emerging class of architectures and a prominent workload: GPGPUs (General-Purpose Graphics Processing Units) and regular expression matching...
Jamin Naghmouchi, Daniele Paolo Scarpazza, Mladen ...
MM
2000
ACM
217views Multimedia» more  MM 2000»
15 years 11 months ago
Design and implementation of the parallel multimedia file system based on message distribution
The two-layered distributed clustered server architecture consisting of a control server and a group of storage servers has been widely used to support multimedia file systems. Wi...
Seung-Ho Park, Si-Yong Park, Gwang Moon Kim, Ki-Do...
DAC
1999
ACM
15 years 11 months ago
IC Test Using the Energy Consumption Ratio
Dynamic-current based test techniques can potentially address the drawbacks of traditional and Iddq test methodologies. The quality of dynamic current based test is degraded by pr...
Wanli Jiang, Bapiraju Vinnakota
DAC
1999
ACM
15 years 11 months ago
Stand-by Power Minimization Through Simultaneous Threshold Voltage Selection and Circuit Sizing
We present a new approach for estimation and optimization of the average stand-by power dissipation in large MOS digital circuits. To overcome the complexity of state dependence i...
Supamas Sirichotiyakul, Tim Edwards, Chanhee Oh, J...