3955 search results - page 352 / 791 » A Transactional Architecture for Simulation |
180
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DAC
2005
ACM
16 years 7 months ago
2005
ACM
The increased deployment of System-on-Chip designs has drawn attention to the limitations of on-chip interconnects. As a potential solution to these limitations, Networks-on -Chip...
177
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ICCAD
2003
IEEE
16 years 3 months ago
2003
IEEE
The Y-architecture for on-chip interconnect is based on pervasive use of 0-, 120-, and 240-degree oriented semi-global and global wiring. Its use of three uniform directions explo...
199
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CASES
2006
ACM
16 years 24 days ago
2006
ACM
We propose an architecture that uses NAND flash memory to reduce main memory power in web server platforms. Our architecture uses a two level file buffer cache composed of a re...
198
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DCOSS
2005
Springer
16 years 11 days ago
2005
Springer
In wireless sensor networks, energy and communication bandwidth are precious resources. Traditionally, layering has been used as a design principle for network stacks; hence routin...
168
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DSD
2003
IEEE
16 years 4 days ago
2003
IEEE
With shrinking feature size of silicon fabrication technology, architects are putting more and more logic into a single die. While one might opt to use these transistors for build...