3955 search results - page 308 / 791 » A Transactional Architecture for Simulation |
190
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GLOBECOM
2009
IEEE
15 years 10 months ago
2009
IEEE
Energy efficiency has become a critical concern in designing high speed packet classification engines for next generation routers. Although TCAM-based solutions can provide high th...
173
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ISCA
2006
IEEE
15 years 6 months ago
2006
IEEE
: Tiled architectures, such as RAW, SmartMemories, TRIPS, and WaveScalar, promise to address several issues facing conventional processors, including complexity, wire-delay, and pe...
162
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OSN
2008
15 years 6 months ago
2008
In this paper, we present a new hybrid optical burst switch architecture (HOBS) that takes advantage of the pre-transmission idle time during lightpath establishment. In dynamic c...
159
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TCOM
2008
15 years 6 months ago
2008
Abstract-- Traditionally, conflict resolution in an inputbuffered switch is solved by finding a matching between inputs and outputs per time slot. To do this, a switch not only nee...
238
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TVLSI
2008
2008
A Design Flow for Architecture Exploration and Implementation of Partially Reconfigurable Processors
15 years 6 months ago
During the last years, the growing application complexity, design, and mask costs have compelled embedded system designers to increasingly consider partially reconfigurable applica...