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ISPASS
2006
IEEE
16 years 22 days ago
Critical path analysis of the TRIPS architecture
Fast, accurate, and effective performance analysis is essential for the design of modern processor architectures and improving application performance. Recent trends toward highly...
Ramadass Nagarajan, Xia Chen, Robert G. McDonald, ...
CODES
2005
IEEE
16 years 10 days ago
Power-smart system-on-chip architecture for embedded cryptosystems
In embedded cryptosystems, sensitive information can leak via timing, power, and electromagnetic channels. We introduce a novel power-smart system-on-chip architecture that provid...
Radu Muresan, Haleh Vahedi, Y. Zhanrong, Stefano G...
IEEEPACT
2005
IEEE
16 years 10 days ago
A Distributed Control Path Architecture for VLIW Processors
VLIW architectures are popular in embedded systems because they offer high-performance processing at low cost and energy. The major problem with traditional VLIW designs is that t...
Hongtao Zhong, Kevin Fan, Scott A. Mahlke, Michael...
INFOCOM
2003
IEEE
16 years 10 hour ago
S-MIP: A Seamless Handoff Architecture for Mobile IP
—As the number of Mobile IP (MIP) [2] users grow, so will the demand for delay sensitive real-time applications, such as audio streaming, that require seamless handoff, namely, a...
Robert Hsieh, Zhe Guang Zhou, Aruna Seneviratne
IPPS
1998
IEEE
15 years 11 months ago
HIPIQS: A High-Performance Switch Architecture Using Input Queuing
Switch-based interconnects are used in a number of application domains including parallel system interconnects, local area networks, and wide area networks. However, very few swit...
Rajeev Sivaram, Craig B. Stunkel, Dhabaleswar K. P...