3955 search results - page 306 / 791 » A Transactional Architecture for Simulation |
175
click to vote
ICCAD
2003
IEEE
16 years 3 months ago
2003
IEEE
— Memory-intensive applications present unique challenges to an ASIC designer in terms of the choice of memory organization, memory size requirements, bandwidth and access latenc...
176
click to vote
ISCA
2009
IEEE
16 years 1 months ago
2009
IEEE
Caching techniques have been an efficient mechanism for mitigating the effects of the processor-memory speed gap. Traditional multi-level SRAM-based cache hierarchies, especially...
214
click to vote
ICC
2007
IEEE
16 years 1 months ago
2007
IEEE
Abstract— Ultra-wideband (UWB) impulse radio is a promising technique for low-power bio-medical communication systems. While a range of analog and digital UWB architectures exist...
142
click to vote
CGO
2006
IEEE
16 years 24 days ago
2006
IEEE
Explicit Data Graph Execution (EDGE) architectures offer the possibility of high instruction-level parallelism with energy efficiency. In EDGE architectures, the compiler breaks ...
153
click to vote
HPCS
2006
IEEE
16 years 23 days ago
2006
IEEE
This paper presents the initial design of the Cyclops-64 (C64) system software infrastructure and tools under development as a joint effort between IBM T.J. Watson Research Center...