Sciweavers

3955 search results - page 302 / 791
» A Transactional Architecture for Simulation
Sort
View
FPGA
2001
ACM
123views FPGA» more  FPGA 2001»
15 years 11 months ago
Mixing buffers and pass transistors in FPGA routing architectures
The routing architecture of an FPGA consists of the length of the wires, the type of switch used to connect wires (buffered, unbuffered, fast or slow) and the topology of the inte...
Mike Sheng, Jonathan Rose
IJWMC
2007
84views more  IJWMC 2007»
15 years 6 months ago
Towards all-IP wireless networks: architectures and resource management mechanism
Future wireless Internet will consist of different wireless technologies that should operate together in an efficient way to provide seamless connectivity to mobile users. The in...
Majid Ghaderi, Raouf Boutaba
DAC
2005
ACM
16 years 7 months ago
Device and architecture co-optimization for FPGA power reduction
Device optimization considering supply voltage Vdd and threshold voltage Vt tuning does not increase chip area but has a great impact on power and performance in the nanometer tec...
Lerong Cheng, Phoebe Wong, Fei Li, Yan Lin, Lei He
MTV
2005
IEEE
100views Hardware» more  MTV 2005»
16 years 9 days ago
A Study of Architecture Description Languages from a Model-based Perspective
Abstract— Owing to the recent trend of using applicationspecific instruction-set processors (ASIP), many Architecture Description Languages (ADLs) have been created. They specif...
Wei Qin, Sharad Malik
JNCA
2007
125views more  JNCA 2007»
15 years 6 months ago
Distributed middleware architectures for scalable media services
The fusion of Multimedia and Internet technology has introduced an ever-increasing demand for large-scale reliable media services. This exposes the scalability limitations of curr...
Vana Kalogeraki, Demetrios Zeinalipour-Yazti, Dimi...