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» A Transactional Architecture for Simulation
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SIGSOFT
2000
ACM
15 years 11 months ago
COM revisited: tool-assisted modelling of an architectural framework
Designing architectural frameworks without the aid of formal modeling is error prone. But, unless supported by analysis, formal modeling is prone to its own class of errors, in wh...
Daniel Jackson, Kevin J. Sullivan
ASPDAC
2009
ACM
137views Hardware» more  ASPDAC 2009»
15 years 10 months ago
Reconfigurable double gate carbon nanotube field effect transistor based nanoelectronic architecture
-- Carbon nanotubes (CNTs) and carbon nanotube field effect transistors (CNFETs) have demonstrated extraordinary properties and are widely accepted as the building blocks of next g...
Bao Liu
FCCM
2009
IEEE
134views VLSI» more  FCCM 2009»
15 years 10 months ago
Efficient Mapping of Hardware Tasks on Reconfigurable Computers Using Libraries of Architecture Variants
Scheduling and partitioning of task graphs on reconfigurable hardware needs to be carefully carried out in order to achieve the best possible performance. In this paper, we demons...
Miaoqing Huang, Vikram K. Narayana, Tarek A. El-Gh...
ASPDAC
2004
ACM
158views Hardware» more  ASPDAC 2004»
15 years 10 months ago
Decode filter cache for energy efficient instruction cache hierarchy in super scalar architectures
Abstract-- The power consumption of microprocessors has been increasing in step with the complexity of each progressive generation. In general purpose processors, this is primarily...
Kugan Vivekanandarajah, Thambipillai Srikanthan, S...
DATE
2004
IEEE
158views Hardware» more  DATE 2004»
15 years 10 months ago
Bandwidth-Constrained Mapping of Cores onto NoC Architectures
We address the design of complex monolithic systems, where processing cores generate and consume a varying and large amount of data, thus bringing the communication links to the e...
Srinivasan Murali, Giovanni De Micheli