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DATE
2010
IEEE
131views Hardware» more  DATE 2010»
15 years 11 months ago
Energy-performance design space exploration in SMT architectures exploiting selective load value predictions
—This paper presents a design space exploration of a selective load value prediction scheme suitable for energyaware Simultaneous Multi-Threaded (SMT) architectures. A load value...
Arpad Gellert, Gianluca Palermo, Vittorio Zaccaria...
ARCS
2006
Springer
15 years 10 months ago
Estimating Energy Consumption for an MPSoC Architectural Exploration
Early energy estimation is increasingly important in MultiProcessor System-On-Chip (MPSoC) design. Applying traditional approaches, which consist in delaying the estimation until t...
Rabie Ben Atitallah, Smaïl Niar, Alain Greine...
ICS
2000
Tsinghua U.
15 years 10 months ago
Characterizing processor architectures for programmable network interfaces
The rapid advancements of networking technology have boosted potential bandwidth to the point that the cabling is no longer the bottleneck. Rather, the bottlenecks lie at the cros...
Patrick Crowley, Marc E. Fiuczynski, Jean-Loup Bae...
ECIR
2004
Springer
15 years 8 months ago
Performance Analysis of Distributed Architectures to Index One Terabyte of Text
We simulate different architectures of a distributed Information Retrieval system on a very large Web collection, in order to work out the optimal setting for a particular set of r...
Fidel Cacheda, Vassilis Plachouras, Iadh Ounis
ISCA
2006
IEEE
123views Hardware» more  ISCA 2006»
15 years 6 months ago
A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks
Packet-based on-chip networks are increasingly being adopted in complex System-on-Chip (SoC) designs supporting numerous homogeneous and heterogeneous functional blocks. These Net...
Jongman Kim, Chrysostomos Nicopoulos, Dongkook Par...