3955 search results - page 265 / 791 » A Transactional Architecture for Simulation |
195
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IEEEPACT
2007
IEEE
16 years 29 days ago
2007
IEEE
Nowadays, multithreaded architectures are becoming more and more popular. In order to evaluate their behavior, several methodologies and metrics have been proposed. A methodology ...
189
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ITNG
2007
IEEE
16 years 26 days ago
2007
IEEE
In this paper, we present several enhanced network techniques which are appropriate for VLSI implementation and have reduced complexity, high throughput, and simple routing algori...
164
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DATE
2006
IEEE
16 years 22 days ago
2006
IEEE
Mesh architectures are used to distribute critical global signals on a chip, such as clock and power/ground. Redundancy created by mesh loops smooths out undesirable variations be...
172
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IPPS
2006
IEEE
16 years 21 days ago
2006
IEEE
In this paper, we present a dynamically reconfigurable cache architecture using adaptive block allocation policy analyzed by means of simulation. Our main objectives are: to propo...
187
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EUROPAR
2005
Springer
16 years 6 days ago
2005
Springer
There are two important hurdles that restrict the scalability of directory-based shared-memory multiprocessors: the directory memory overhead and the long L2 miss latencies due to ...