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SIGIR
1996
ACM
15 years 10 months ago
Performance Evaluation of a Distributed Architecture for Information Retrieval
Information explosion across the Internet and elsewhere offers access to an increasing number of document collections. In order for users to e ectively access these collections, i...
Brendon Cahoon, Kathryn S. McKinley
CODES
2006
IEEE
15 years 8 months ago
Architectural support for safe software execution on embedded processors
The lack of memory safety in many popular programming languages, including C and C++, has been a cause for great concern in the realm of software reliability, verification, and mo...
Divya Arora, Anand Raghunathan, Srivaths Ravi, Nir...
SIGARCH
2008
97views more  SIGARCH 2008»
15 years 6 months ago
SP-NUCA: a cost effective dynamic non-uniform cache architecture
1 This paper presents a simple but effective method to reduce on-chip access latency and improve core isolation in CMP Non-Uniform Cache Architectures (NUCA). The paper introduces ...
Javier Merino, Valentin Puente, Pablo Prieto, Jos&...
HPCA
2009
IEEE
16 years 7 months ago
A novel architecture of the 3D stacked MRAM L2 cache for CMPs
Magnetic Random Access Memory (MRAM) is considered to be a promising future memory technology due to its low leakage power, high density and fast read speed. The heterogeneous int...
Guangyu Sun, Xiangyu Dong, Yuan Xie, Jian Li, Yira...
186
Voted
CF
2006
ACM
16 years 19 days ago
Dynamic thread assignment on heterogeneous multiprocessor architectures
In a multi-programmed computing environment, threads of execution exhibit different runtime characteristics and hardware resource requirements. Not only do the behaviors of distin...
Michela Becchi, Patrick Crowley