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ASPLOS
2006
ACM
16 years 19 days ago
A spatial path scheduling algorithm for EDGE architectures
Growing on-chip wire delays are motivating architectural features that expose on-chip communication to the compiler. EDGE architectures are one example of communication-exposed mi...
Katherine E. Coons, Xia Chen, Doug Burger, Kathryn...
IPPS
2010
IEEE
15 years 4 months ago
Acceleration of spiking neural networks in emerging multi-core and GPU architectures
Recently, there has been strong interest in large-scale simulations of biological spiking neural networks (SNN) to model the human brain mechanisms and capture its inference capabi...
Mohammad A. Bhuiyan, Vivek K. Pallipuram, Melissa ...
ANCS
2011
ACM
14 years 6 months ago
A Scalability Study of Enterprise Network Architectures
The largest enterprise networks already contain hundreds of thousands of hosts. Enterprise networks are composed of Ethernet subnets interconnected by IP routers. These routers re...
Brent Stephens, Alan L. Cox, Scott Rixner, T. S. E...
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GLOBECOM
2009
IEEE
16 years 1 months ago
PreDA: Predicate Routing for DTN Architectures over MANET
—We consider a Delay Tolerant Network (DTN) whose users (nodes) are connected by an underlying Mobile Ad hoc Network (MANET) substrate. Users can declaratively express high-level...
Flavio Esposito, Ibrahim Matta
ISSTA
2006
ACM
16 years 18 days ago
Towards supporting the architecture design process through evaluation of design alternatives
This paper addresses issues involved when an architect explore alternative designs including non-functional requirements; in our approach, non-functional requirements are expresse...
Lihua Xu, Scott A. Hendrickson, Eric Hettwer, Hada...