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FPGA
2003
ACM
120views FPGA» more  FPGA 2003»
15 years 12 months ago
Architecture evaluation for power-efficient FPGAs
This paper presents a flexible FPGA architecture evaluation framework, named fpgaEVA-LP, for power efficiency analysis of LUT-based FPGA architectures. Our work has several contri...
Fei Li, Deming Chen, Lei He, Jason Cong
ICCAD
1999
IEEE
115views Hardware» more  ICCAD 1999»
15 years 11 months ago
Fast performance analysis of bus-based system-on-chip communication architectures
This paper addresses the problem of efficient and accurate performance analysis to drive the exploration and design of bus-based System-on-Chip (SOC) communication architectures. ...
Kanishka Lahiri, Anand Raghunathan, Sujit Dey
CGO
2004
IEEE
15 years 10 months ago
VHC: Quickly Building an Optimizer for Complex Embedded Architectures
To meet the high demand for powerful embedded processors, VLIW architectures are increasingly complex (e.g., multiple clusters), and moreover, they now run increasingly sophistica...
Michael Dupré, Nathalie Drach, Olivier Tema...
ISQED
2007
IEEE
160views Hardware» more  ISQED 2007»
16 years 28 days ago
On-Chip Inductance in X Architecture Enabled Design
The inductance effects become significant for sub-100nm process designs due to increasing interconnect lengths, lower interconnect resistance values and fast signal transition tim...
Santosh Shah, Arani Sinha, Li Song, Narain D. Aror...
183
Voted
SIGCOMM
1998
ACM
15 years 11 months ago
The MASC/BGMP Architecture for Inter-Domain Multicast Routing
Multicast routing enables e cient data distribution to multiple recipients. However, existing work has concentrated on extending single-domain techniques to wide-area networks, ra...
Satish Kumar, Pavlin Radoslavov, David Thaler, Cen...