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ISQED
2007
IEEE
140views Hardware» more  ISQED 2007»
16 years 28 days ago
Leakage-Conscious Architecture-Level Power Estimation for Partitioned and Power-Gated SRAM Arrays
We propose a methodology and power models for an accurate high-level power estimation of physically partitioned and power-gated SRAM arrays. The models offer accurate estimation o...
Minh Quang Do, Mindaugas Drazdziulis, Per Larsson-...
SIPS
2007
IEEE
16 years 27 days ago
Sphere Decoding for Multiprocessor Architectures
Motivated by the need for high throughput sphere decoding for multipleinput-multiple-output (MIMO) communication systems, we propose a parallel depth-first sphere decoding (PDSD)...
Qi Qi, Chaitali Chakrabarti
ISCAS
2005
IEEE
140views Hardware» more  ISCAS 2005»
16 years 7 days ago
Low energy asynchronous architectures
: Asynchronous circuits are often presented as a means of achieving low power operation. We investigate their suitability for low-energy applications, where long battery life and d...
Ilya Obridko, Ran Ginosar
ISCA
1990
IEEE
186views Hardware» more  ISCA 1990»
15 years 10 months ago
Adaptive Software Cache Management for Distributed Shared Memory Architectures
An adaptive cache coherence mechanism exploits semantic information about the expected or observed access behavior of particular data objects. We contend that, in distributed shar...
John K. Bennett, John B. Carter, Willy Zwaenepoel
179
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ISLPED
1995
ACM
116views Hardware» more  ISLPED 1995»
15 years 10 months ago
Activity-sensitive architectural power analysis for the control path
Prompted by demands for portability and low-cost packaging, the electronics industry has begun to view power consumption as a critical design criteria. As such there is a growing ...
Paul E. Landman, Jan M. Rabaey