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VLSID
2006
IEEE
153views VLSI» more  VLSID 2006»
16 years 7 months ago
An Asynchronous Interconnect Architecture for Device Security Enhancement
We present a new style of long-distance, on-chip interconnect, based loosely on the asynchronous GasP architecture. It has a number of advantages over conventional designs, the mo...
Simon Hollis, Simon W. Moore
HPCA
2001
IEEE
16 years 7 months ago
Automatically Mapping Code on an Intelligent Memory Architecture
This paper presents an algorithm to automatically map code on a generic intelligent memory system that consists of a host processor and a simpler memory processor. To achieve high...
Jaejin Lee, Yan Solihin, Josep Torrellas
ICCD
2004
IEEE
129views Hardware» more  ICCD 2004»
16 years 3 months ago
Cache Array Architecture Optimization at Deep Submicron Technologies
A cache access time model, PRACTICS (PRedictor of Access and Cycle TIme for Cache Stack), has been developed to optimize the memory array architecture for the minimum access and c...
Annie (Yujuan) Zeng, Kenneth Rose, Ronald J. Gutma...
DSD
2008
IEEE
136views Hardware» more  DSD 2008»
16 years 1 months ago
Flexible Baseband Architectures for Future Wireless Systems
— The mobile communication systems today, have different radio spectrum, radio access technologies, and protocol stacks depending on the network being utilized. This gives rise t...
Najam-ul-Islam Muhammad, Rizwan Rasheed, Renaud Pa...
ICPADS
2008
IEEE
16 years 1 months ago
Quarc: A Novel Network-On-Chip Architecture
This paper introduces the Quarc NoC, a novel NoC architecture inspired by the Spidergon NoC [16]. The Quarc scheme significantly outperforms the Spidergon NoC through balancing t...
Mahmoud Moadeli, Wim Vanderbauwhede, Ali Shahrabi