1727 search results - page 139 / 346 » A Technique for Large Automated Mechanism Design Problems |
130
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DAC
2000
ACM
16 years 7 months ago
2000
ACM
Due to the large die sizes and tight relative clock skew margins, the impact of interconnect manufacturing variations on the clock skew in today's gigahertz microprocessors c...
143
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DAC
2008
ACM
16 years 7 months ago
2008
ACM
FPGA application developers often attempt to use pipelining, Cslowing and retiming to improve the performance of their designs. Unfortunately, such registered netlists present a f...
147
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DAC
2005
ACM
16 years 7 months ago
2005
ACM
In this paper, we present a new linear-time retiming algorithm that produces near-optimal results. Our implementation is specifically targeted at Altera's Stratix [1] FPGAbas...
156
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DAC
2009
ACM
16 years 7 months ago
2009
ACM
Abstract--To reduce chip-scale topography variation in Chemical Mechanical Polishing (CMP) process, dummy fill is widely used to improve the layout density uniformity. Previous res...
209
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SECON
2007
IEEE
16 years 23 days ago
2007
IEEE
—Increasingly many wireless sensor network deployments are using harvested environmental energy to extend system lifetime. Because the temporal profiles of such energy sources e...