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» A Technique for Large Automated Mechanism Design Problems
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DFT
2003
IEEE
113views VLSI» more  DFT 2003»
15 years 11 months ago
Buffer and Controller Minimisation for Time-Constrained Testing of System-On-Chip
Test scheduling and Test Access Mechanism (TAM) design are two important tasks in the development of a System-on-Chip (SOC) test solution. Previous test scheduling techniques assu...
Anders Larsson, Erik Larsson, Petru Eles, Zebo Pen...
CADE
2005
Springer
16 years 6 months ago
Proof Planning for First-Order Temporal Logic
Proof planning is an automated reasoning technique which improves proof search by raising it to a meta-level. In this paper we apply proof planning to First-Order Linear Temporal L...
Claudio Castellini, Alan Smaill
DAC
2007
ACM
16 years 7 months ago
Variation Resilient Low-Power Circuit Design Methodology using On-Chip Phase Locked Loop
This paper presents a variation resilient circuit design technique for maintaining parametric yield of design under inherent variation in process parameters. We propose to utilize...
Kunhyuk Kang, Kee-Jong Kim, Kaushik Roy
CADE
2008
Springer
16 years 6 months ago
Exploring Model-Based Development for the Verification of Real-Time Java Code
Many safety- and security-critical systems are real-time systems and, as a result, tools and techniques for verifying real-time systems are extremely important. Simulation and test...
Niusha Hakimipour, Paul A. Strooper, Roger Duke
IPPS
2006
IEEE
16 years 15 days ago
FPGA implementation of a license plate recognition SoC using automatically generated streaming accelerators
Modern FPGA platforms provide the hardware and software infrastructure for building a bus-based System on Chip (SoC) that meet the applications requirements. The designer can cust...
Nikolaos Bellas, Sek M. Chai, Malcolm Dwyer, Dan L...