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CAV
1999
Springer
92views Hardware» more  CAV 1999»
15 years 10 months ago
Latency Insensitive Protocols
The theory of latency insensitive design is presented as the foundation of a new correct by construction methodology to design very large digital systems by assembling blocks of In...
Luca P. Carloni, Kenneth L. McMillan, Alberto L. S...
SIGCOMM
2010
ACM
15 years 6 months ago
Efficient error estimating coding: feasibility and applications
Motivated by recent emerging systems that can leverage partially correct packets in wireless networks, this paper investigates the novel concept of error estimating codes (EEC). W...
Binbin Chen, Ziling Zhou, Yuda Zhao, Haifeng Yu
DATE
2004
IEEE
126views Hardware» more  DATE 2004»
15 years 10 months ago
Generalized Latency-Insensitive Systems for Single-Clock and Multi-Clock Architectures
Latency-insensitive systems were recently proposed by Carloni et al. as a correct-by-construction methodology for single-clock system-on-a-chip (SoC) design using predesigned IP b...
Montek Singh, Michael Theobald
DANCE
2002
IEEE
15 years 11 months ago
Active Network Vision and Reality: Lessons from a Capsule-Based System
Although active networks have generated much debate in the research community, on the whole there has been little hard evidence to inform this debate. This paper aims to redress t...
David Wetherall
VRML
1999
ACM
15 years 10 months ago
VIRTUS: A Collaborative Multi-User Platform
VRML is a file format for the description of dynamic scene graphs containing 3D objects with their visual appearance, multimedia content, an event model, and scripting capabilitie...
Kurt Saar