1283 search results - page 177 / 257 » A Survey on Temporal Logics |
305
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NFM
2011
15 years 1 months ago
2011
Synthesis of finite-state machines from linear-time temporal logic (LTL) formulas is an important formal specification debugging technique for reactive systems and can quickly ge...
181
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TII
2010
15 years 1 months ago
2010
In this paper, we develop an automated framework for formal verification of timed continuous Petri nets (ContPNs). Specifically, we consider two problems: (1) given an initial set ...
185
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DATE
2009
IEEE
16 years 1 months ago
2009
IEEE
—A large part of a modern SOC’s debug complexity resides in the interaction between the main system components. ion-level debug moves the abstraction level of the debug process...
154
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ATVA
2007
Springer
16 years 14 days ago
2007
Springer
Message Sequence Charts (MSCs) and High-level Message Sequence Charts (HMSCs) are formalisms used to describe scenarios of message passing protocols. We propose using Allen’s log...
165
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POLICY
2007
Springer
16 years 12 days ago
2007
Springer
—There is increasing demand for running interacting applications in a secure and controllable way on mobile devices. Such demand is not fully supported by the Java/.NET security ...