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» A Study on Impact of Leakage Current on Dynamic Power
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ICCD
2007
IEEE
111views Hardware» more  ICCD 2007»
16 years 3 months ago
On modeling impact of sub-wavelength lithography on transistors
As the VLSI technology marches beyond 65 and 45nm process technologies, variation in gate length has a direct impact on leakage and performance of CMOS transistors. Due to sub-wav...
Aswin Sreedhar, Sandip Kundu
CASES
2008
ACM
15 years 8 months ago
Multiple sleep mode leakage control for cache peripheral circuits in embedded processors
This paper proposes a combination of circuit and architectural techniques to maximize leakage power reduction in embedded processor on-chip caches. It targets cache peripheral cir...
Houman Homayoun, Mohammad A. Makhzan, Alexander V....
ISLPED
2009
ACM
168views Hardware» more  ISLPED 2009»
16 years 16 days ago
Low power circuit design based on heterojunction tunneling transistors (HETTs)
The theoretical lower limit of subthreshold swing in MOSFETs (60 mV/decade) significantly restricts low voltage operation since it results in a low ON to OFF current ratio at low ...
Daeyeon Kim, Yoonmyung Lee, Jin Cai, Isaac Lauer, ...
ISQED
2010
IEEE
151views Hardware» more  ISQED 2010»
16 years 27 days ago
Leakage temperature dependency modeling in system level analysis
Abstract— As the semiconductor technology continues its marching toward the deep sub-micron domain, the strong relation between leakage current and temperature becomes critical i...
Huang Huang, Gang Quan, Jeffrey Fan
ISLPED
2006
ACM
83views Hardware» more  ISLPED 2006»
16 years 1 hour ago
Considering process variations during system-level power analysis
Process variations will increasingly impact the operational characteristics of integrated circuits in nanoscale semiconductor technologies. Researchers have proposed various desig...
Saumya Chandra, Kanishka Lahiri, Anand Raghunathan...