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» A Software Architecture for Industrial Automation
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DAC
2003
ACM
16 years 7 months ago
Performance-impact limited area fill synthesis
Chemical-mechanical planarization (CMP) and other manufacturing steps in very deep-submicron VLSI have varying effects on device and interconnect features, depending on the local ...
Yu Chen, Puneet Gupta, Andrew B. Kahng
DAC
2003
ACM
16 years 7 months ago
Clock-tree power optimization based on RTL clock-gating
As power consumption of the clock tree in modern VLSI designs tends to dominate, measures must be taken to keep it under control. This paper introduces an approach for reducing cl...
Monica Donno, Alessandro Ivaldi, Luca Benini, Enri...
DAC
2003
ACM
16 years 7 months ago
Learning from BDDs in SAT-based bounded model checking
Bounded Model Checking (BMC) based on Boolean Satisfiability (SAT) procedures has recently gained popularity as an alternative to BDD-based model checking techniques for finding b...
Aarti Gupta, Malay K. Ganai, Chao Wang, Zijiang Ya...
DAC
2003
ACM
16 years 7 months ago
Test cost reduction for SOCs using virtual TAMs and lagrange multipliers
Recent advances in tester technology have led to automatic test equipment (ATE) that can operate at up to several hundred MHz. However, system-on-chip (SOC) scan chains typically ...
Anuja Sehgal, Vikram Iyengar, Mark D. Krasniewski,...
DAC
2003
ACM
16 years 7 months ago
An O(nlogn) time algorithm for optimal buffer insertion
The classic algorithm for optimal buffer insertion due to van Ginneken has time and space complexity O(n2 ), where n is the number of possible buffer positions. We present a new a...
Weiping Shi, Zhuo Li