188 search results - page 31 / 38 » A Simulator for the Reconfigurable Mesh Architecture |
134
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DAC
2008
ACM
16 years 7 months ago
2008
ACM
FPGA application developers often attempt to use pipelining, Cslowing and retiming to improve the performance of their designs. Unfortunately, such registered netlists present a f...
147
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ESTIMEDIA
2004
Springer
15 years 9 months ago
2004
Springer
This paper presents a new adaptive scheme to reduce the computation energy of the discrete cosine transform (DCT) architecture for image/video coding. The scheme employs the noise ...
169
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BIBE
2007
IEEE
15 years 7 months ago
2007
IEEE
In this paper we describe our design and characterization of a co-processor architecture to accelerate median-based phylogenetic reconstruction for generearrangement data. Our curr...
146
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ICCAD
2003
IEEE
16 years 2 months ago
2003
IEEE
The Y-architecture for on-chip interconnect is based on pervasive use of 0-, 120-, and 240-degree oriented semi-global and global wiring. Its use of three uniform directions explo...
177
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FPGA
2006
ACM
15 years 9 months ago
2006
ACM
The development of Reed-Solomon (RS) codes has allowed for improved data transmission over a variety of communication media. Although Reed-Solomon decoding provides a powerful def...