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» A Semantics for Multiprocessor Systems
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ISCA
1998
IEEE
114views Hardware» more  ISCA 1998»
15 years 11 months ago
The MIT Alewife Machine: Architecture and Performance
Alewife is a multiprocessor architecture that supports up to 512 processing nodes connected over a scalable and cost-effective mesh network at a constant cost per node. The MIT Al...
Anant Agarwal, Ricardo Bianchini, David Chaiken, K...
IPPS
1997
IEEE
15 years 11 months ago
Dynamic Processor Scheduling with Client Resources for Fast Multi-Resolution WWW Image Browsing
WWW-based Internet information service has grown enormously during the last few years, and major performance bottlenecks have been caused by WWW server and Internet bandwidth inad...
Daniel Andresen, Tao Yang, David Watson, Athanassi...
SWAT
1994
Springer
94views Algorithms» more  SWAT 1994»
15 years 10 months ago
On Self-Stabilizing Wait-Free Clock Synchronization
Protocols which can tolerate any number of processors failing by ceasing operation for an unbounded number of steps and resuming operation (with or) without knowing that they were...
Marina Papatriantafilou, Philippas Tsigas
SOSP
1989
ACM
15 years 7 months ago
Performance of Firefly RPC
In this paper, we report on the performance of the remote procedure call implementation for the Firefly multiprocessor and analyze the implementation to account precisely for all ...
Michael D. Schroeder, Michael Burrows
SAMOS
2010
Springer
15 years 5 months ago
Interleaving granularity on high bandwidth memory architecture for CMPs
—Memory bandwidth has always been a critical factor for the performance of many data intensive applications. The increasing processor performance, and the advert of single chip m...
Felipe Cabarcas, Alejandro Rico, Yoav Etsion, Alex...