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CASES
2008
ACM
15 years 8 months ago
Efficiency and scalability of barrier synchronization on NoC based many-core architectures
Interconnects based on Networks-on-Chip are an appealing solution to address future microprocessor designs where, very likely, hundreds of cores will be connected on a single chip...
Oreste Villa, Gianluca Palermo, Cristina Silvano
MSS
2003
IEEE
93views Hardware» more  MSS 2003»
15 years 11 months ago
IP SAN - From iSCSI to IP-Addressable Ethernet Disks
The initial iSCSI products provide a means to connect FC SAN islands across IP networks. This paper describes the implementation of an IP-SAN where the disk subsystem is a virtual...
Peter Wang, Robert E. Gilligan, Henry Green, Jeff ...
ISCA
2011
IEEE
365views Hardware» more  ISCA 2011»
14 years 9 months ago
Kilo-NOC: a heterogeneous network-on-chip architecture for scalability and service guarantees
Today’s chip-level multiprocessors (CMPs) feature up to a hundred discrete cores, and with increasing levels of integration, CMPs with hundreds of cores, cache tiles, and specia...
Boris Grot, Joel Hestness, Stephen W. Keckler, Onu...
COMCOM
2006
115views more  COMCOM 2006»
15 years 6 months ago
Energy-efficient scheduling and hybrid communication architecture for underwater littoral surveillance
There exists a high demand for reliable, high capacity underwater acoustic networks to allow efficient data gathering and information exchange. This is evidenced by significant re...
Mihaela Cardei
ICANN
2007
Springer
16 years 4 days ago
SpikeStream: A Fast and Flexible Simulator of Spiking Neural Networks
SpikeStream is a new simulator of biologically structured spiking neural networks that can be used to edit, display and simulate up to 100,000 neurons. This simulator uses a combin...
David Gamez