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DATE
2009
IEEE
113views Hardware» more  DATE 2009»
16 years 1 months ago
Scalable compile-time scheduler for multi-core architectures
As the number of cores continues to grow in both digital signal and general purpose processors, tools which perform automatic scheduling from model-based designs are of increasing...
Maxime Pelcat, Pierrick Menuet, Slaheddine Aridhi,...
TCSV
2002
103views more  TCSV 2002»
15 years 6 months ago
A scalable and programmable architecture for 2-D DWT decoding
The compression of still images by means of the discrete wavelet transform (DWT), adopted in the JPEG-2000 and MPEG-4 standards, is becoming more and more widespread because it yie...
Massimo Ravasi, L. Tenze, Marco Mattavelli
ISCA
2011
IEEE
287views Hardware» more  ISCA 2011»
14 years 10 months ago
Scalable power control for many-core architectures running multi-threaded applications
Optimizing the performance of a multi-core microprocessor within a power budget has recently received a lot of attention. However, most existing solutions are centralized and cann...
Kai Ma, Xue Li, Ming Chen, Xiaorui Wang
TCOM
2008
92views more  TCOM 2008»
15 years 6 months ago
Mailbox switch: a scalable two-stage switch architecture for conflict resolution of ordered packets
Abstract-- Traditionally, conflict resolution in an inputbuffered switch is solved by finding a matching between inputs and outputs per time slot. To do this, a switch not only nee...
Cheng-Shang Chang, Duan-Shin Lee, Ying-Ju Shih, Ch...
SIGMETRICS
2002
ACM
101views Hardware» more  SIGMETRICS 2002»
15 years 6 months ago
A performance study of Bistro, a scalable upload architecture
Hot spots are a major obstacle to achieving scalability in the Internet. We have observed that the existence of hot spots in upload applications (whose examples include submission...
William C. Cheng, Cheng-Fu Chou, Leana Golubchik, ...