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178
Voted
ISCA
2009
IEEE
146views Hardware» more  ISCA 2009»
16 years 1 months ago
Multi-execution: multicore caching for data-similar executions
While microprocessor designers turn to multicore architectures to sustain performance expectations, the dramatic increase in parallelism of such architectures will put substantial...
Susmit Biswas, Diana Franklin, Alan Savage, Ryan D...
192
Voted
VLSID
2006
IEEE
192views VLSI» more  VLSID 2006»
16 years 26 days ago
Beyond RTL: Advanced Digital System Design
This tutorial focuses on advanced techniques to cope with the complexity of designing modern digital chips which are complete systems often containing multiple processors, complex...
Shiv Tasker, Rishiyur S. Nikhil
203
Voted
INFOCOM
2003
IEEE
16 years 4 days ago
Associative Search in Peer to Peer Networks: Harnessing Latent Semantics
— The success of a P2P file-sharing network highly depends on the scalability and versatility of its search mechanism. Two particularly desirable search features are scope (abil...
Edith Cohen, Amos Fiat, Haim Kaplan
176
Voted
SIGCOMM
2003
ACM
16 years 3 days ago
Scaling internet routers using optics
Routers built around a single-stage crossbar and a centralized scheduler do not scale, and (in practice) do not provide the throughput guarantees that network operators need to ma...
Isaac Keslassy, Shang-Tse Chuang, Kyoungsik Yu, Da...
ASPLOS
1998
ACM
15 years 11 months ago
Space-Time Scheduling of Instruction-Level Parallelism on a Raw Machine
Advances in VLSI technology will enable chips with over a billion transistors within the next decade. Unfortunately, the centralized-resource architectures of modern microprocesso...
Walter Lee, Rajeev Barua, Matthew Frank, Devabhakt...