—One of the major design verification challenges in the development of Anton, a massively parallel special-purpose machine for molecular dynamics, was to provide evidence that co...
John P. Grossman, John K. Salmon, Richard C. Ho, D...
Late CMOS scaling reduces device reliability, and existing work has studied the permanent SER (soft error rate) for configuration memory in FPGA extensively. In this paper, we sh...
– Identifying worst-case voltage drop conditions in every module supplied by the power grid is a crucial problem in modern IC design. In this paper we develop a novel methodology...
Nestoras E. Evmorfopoulos, Dimitris P. Karampatzak...
Multiple clock cycles are needed to cross the global interconnects for multi-gigahertz designs in nanometer technologies. For synchronous design, this requires the consideration o...
Jason Cong, Yiping Fan, Guoling Han, Xun Yang, Zhi...
We introduce Xampling, a design methodology for analog compressed sensing in which we sample analog bandlimited signals at rates far lower than Nyquist, without loss of informatio...