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GD
1999
Springer
15 years 10 months ago
Centrality in Policy Network Drawings
—We introduce a network visualization technique that supports an analytical method applied in the social sciences. Policy network analysis is an approach to study policy making s...
Ulrik Brandes, Patrick Kenis, Dorothea Wagner
ISORC
2009
IEEE
16 years 1 months ago
Marte CCSL to Execute East-ADL Timing Requirements
In the automotive domain, several loosely-coupled Architecture Description Languages (ADLs) compete to proet of abstract modeling and analysis services on top of the implementatio...
Frédéric Mallet, Marie-Agnès ...
WSC
1997
15 years 7 months ago
Efficient Instruction Cache Simulation and Execution Profiling with a Threaded-Code Interpreter
We present an extension to an existing SPARC V8 instruction set simulator, SimICS, to support accurate profiling of branches and instruction cache misses. SimICS had previously su...
Peter S. Magnusson
CJ
2006
84views more  CJ 2006»
15 years 6 months ago
Instruction Level Parallelism through Microthreading - A Scalable Approach to Chip Multiprocessors
Most microprocessor chips today use an out-of-order instruction execution mechanism. This mechanism allows superscalar processors to extract reasonably high levels of instruction ...
Kostas Bousias, Nabil Hasasneh, Chris R. Jesshope
FTDCS
1997
IEEE
15 years 10 months ago
Toward globally optimal resource management in large-scale real-time distributed computer systems
: This paper discusses the issues and promising approaches in (1) obtaining rigorous specifications of the quality-of-service (QoS) requirements associated with application functio...
K. H. Kim