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» A Refactoring Approach to Parallelism
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ASAP
2006
IEEE
106views Hardware» more  ASAP 2006»
16 years 22 days ago
Throughput Optimized SHA-1 Architecture Using Unfolding Transformation
In this paper, we analyze the theoretical delay bound of the SHA-1 algorithm and propose architectures to achieve high throughput hardware implementations which approach this boun...
Yong Ki Lee, Herwin Chan, Ingrid Verbauwhede
CCGRID
2006
IEEE
16 years 22 days ago
Integrating Gridcomputing and Metamodeling
Simulation and optimization of complex mechanical and electronical systems is a very time consuming and computationally intensive task. Therefore, metamodeling techniques are ofte...
Dirk Gorissen, Wouter Hendrickx, Karel Crombecq, T...
DATE
2006
IEEE
86views Hardware» more  DATE 2006»
16 years 22 days ago
Synthesis of system verilog assertions
In recent years, Assertion-Based Verification is being widely accepted as a key technology in the pre-silicon validation of system-on-chip(SOC) designs. The System Verilog langua...
Sayantan Das, Rizi Mohanty, Pallab Dasgupta, P. P....
DATE
2006
IEEE
108views Hardware» more  DATE 2006»
16 years 22 days ago
Architectural and technology influence on the optimal total power consumption
In this paper, an approximated closed-form total power consumption equation for circuits working at their optimal supply and threshold voltage is presented. Comparisons of this fo...
Christian Schuster, Jean-Luc Nagel, Christian Pigu...
EDOC
2006
IEEE
16 years 22 days ago
Business Continuity Model. Regeneration System for Manufacturing Components
At present, with the expansion of information technologies at the industry, it is vital to implant proactive, self-managed systems that ensure continuous operation and, therefore,...
Diego Marcos-Jorquera, Francisco Maciá P&ea...