4889 search results - page 474 / 978 » A Refactoring Approach to Parallelism |
171
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IPPS
2009
IEEE
16 years 1 months ago
2009
IEEE
DTA (Decoupled Threaded Architecture) is designed to exploit fine/medium grained Thread Level Parallelism (TLP) by using a distributed hardware scheduling unit and relying on exi...
184
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PVM
2009
Springer
16 years 1 months ago
2009
Springer
Abstract. Most parallel systems on which MPI is used are now hierarchical: some processors are much closer to others in terms of interconnect performance. One of the most common su...
189
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ICASSP
2008
IEEE
16 years 1 months ago
2008
IEEE
Multiple memory banks design is employed in many high performance DSP processors. This architectural feature supports higher memory bandwidth by allowing multiple data memory acce...
164
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ICPP
2008
IEEE
16 years 1 months ago
2008
IEEE
—Transactional Memory (TM) takes responsibility for concurrent, atomic execution of labeled regions of code, freeing the programmer from the need to manage locks. Typical impleme...
172
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IPPS
2008
IEEE
16 years 1 months ago
2008
IEEE
While desktop grids are attractive platforms for executing parallel applications, their volatile nature has often limited their use to so-called “high-throughput” applications...