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ASPDAC
1995
ACM
77views Hardware» more  ASPDAC 1995»
15 years 10 months ago
A scheduling algorithm for synthesis of bus-partitioned architectures
- Due to efficient interconnect structure and internal parallelism bus-partitioned architectures are very beneficial for sub-micron chip design. This paper presents a new approach ...
Vasily G. Moshnyaga, Fumiaki Ohbayashi, Keikichi T...
PC
2007
141views Management» more  PC 2007»
15 years 6 months ago
Physically based simulation of cloth on distributed memory architectures
Physically based simulation of cloth in virtual environments is a computationally demanding problem. It involves modeling the internal material properties of the textile (physical...
Bernhard Thomaszewski, Wolfgang Blochinger
IPPS
2009
IEEE
16 years 1 months ago
A metascalable computing framework for large spatiotemporal-scale atomistic simulations
A metascalable (or “design once, scale on new architectures”) parallel computing framework has been developed for large spatiotemporal-scale atomistic simulations of materials...
Ken-ichi Nomura, Richard Seymour, Weiqiang Wang, H...
LCPC
2005
Springer
16 years 3 days ago
Titanium Performance and Potential: An NPB Experimental Study
Titanium is an explicitly parallel dialect of JavaTM designed for high-performance scientific programming. It offers objectorientation, strong typing, and safe memory management...
Kaushik Datta, Dan Bonachea, Katherine A. Yelick
ARC
2007
Springer
150views Hardware» more  ARC 2007»
15 years 10 months ago
MT-ADRES: Multithreading on Coarse-Grained Reconfigurable Architecture
The coarse-grained reconfigurable architecture ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) and its compiler offer high instruction-level parallelism (ILP)...
Kehuai Wu, Andreas Kanstein, Jan Madsen, Mladen Be...