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ISMVL
2010
IEEE
188views Hardware» more  ISMVL 2010»
15 years 11 months ago
MDGs Reduction Technique Based on the HOL Theorem Prover
—Multiway Decision Graphs (MDGs) subsume Binary Decision Diagrams (BDDs) and extend them by a first-order formulae suitable for model checking of data path circuits. In this pap...
Sa'ed Abed, Otmane Aït Mohamed
DATE
2002
IEEE
94views Hardware» more  DATE 2002»
15 years 11 months ago
Exact Grading of Multiple Path Delay Faults
The problem of fault grading for multiple path delay faults is studied and a method of obtaining the exact coverage is presented. The faults covered are represented and manipulate...
Saravanan Padmanaban, Spyros Tragoudas
EICS
2009
ACM
15 years 10 months ago
MoLIC designer: towards computational support to hci design with MoLIC
MoLIC, a modeling language for designing interaction as a metaphor of conversation, was proposed to allow designers to build a blueprint of all interaction that may take place whe...
Ugo Braga Sangiorgi, Simone Diniz Junqueira Barbos...
ICCAD
1996
IEEE
119views Hardware» more  ICCAD 1996»
15 years 10 months ago
An algorithm for synthesis of system-level interface circuits
We describe an algorithm for the synthesis and optimization of interface circuits for embedded system components such as microprocessors, memory ASIC, and network subsystems with ...
Ki-Seok Chung, Rajesh K. Gupta, C. L. Liu
APN
2006
Springer
15 years 10 months ago
ArgoSPE: Model-Based Software Performance Engineering
Stochastic Petri nets (SPNs) have been proved useful for the quantitative analysis of systems. This paper introduces ArgoSPE, a tool for the performance evaluation of software syst...
Elena Gómez-Martínez, José Me...