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ISPASS
2009
IEEE
16 years 1 months ago
GARNET: A detailed on-chip network model inside a full-system simulator
Until very recently, microprocessor designs were computation-centric. On-chip communication was frequently ignored. This was because of fast, single-cycle on-chip communication. T...
Niket Agarwal, Tushar Krishna, Li-Shiuan Peh, Nira...
TECS
2008
122views more  TECS 2008»
15 years 6 months ago
Quantitative analysis of the speed/accuracy trade-off in transaction level modeling
tion. Transaction Level Modeling (TLM) has been proposed to abstract communication for highspeed system simulation and rapid design space exploration. Although being widely accepte...
Gunar Schirner, Rainer Dömer
SOSP
2007
ACM
16 years 3 months ago
SecVisor: a tiny hypervisor to provide lifetime kernel code integrity for commodity OSes
We propose SecVisor, a tiny hypervisor that ensures code integrity for commodity OS kernels. In particular, SecVisor ensures that only approved code can execute in kernel mode ove...
Arvind Seshadri, Mark Luk, Ning Qu, Adrian Perrig
SYSTOR
2010
ACM
15 years 11 months ago
On the DMA mapping problem in direct device assignment
I/O intensive workloads running in virtual machines can suffer massive performance degradation. Direct assignment of I/O devices to virtual machines is the best performing I/O vir...
Ben-Ami Yassour, Muli Ben-Yehuda, Orit Wasserman
RTCSA
1998
IEEE
15 years 10 months ago
Partition Scheduling in APEX Runtime Environment for Embedded Avionics Software
Advances in the computer technology encouraged the avionics industry to replace the federated design of control units with an integrated suite of control modules that share the co...
Yann-Hang Lee, Daeyoung Kim, Mohamed F. Younis, Je...