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» A Performance Process Maturity Model
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FPGA
2003
ACM
161views FPGA» more  FPGA 2003»
15 years 12 months ago
Implementation of BEE: a real-time large-scale hardware emulation engine
This paper describes the hardware implementation of a real-time, large-scale, multi-chip FPGA (Field Programmable Gate Array) based emulation engine with a capacity of 10 million ...
Chen Chang, Kimmo Kuusilinna, Brian C. Richards, R...
ICTAI
2000
IEEE
15 years 11 months ago
Designing a learning-automata-based controller for client/server systems: a methodology
Abstract— Polling policies have been introduced to simplify the accessing process in client/server systems by a centralized control access scheme. This paper considers a client/s...
Georgios I. Papadimitriou, Athena Vakali, Andreas ...
IPPS
2000
IEEE
15 years 11 months ago
Using Switch Directories to Speed Up Cache-to-Cache Transfers in CC-NUMA Multiprocessors
In this paper, we propose a novel hardware caching technique, called switch directory, to reduce the communication latency in CC-NUMA multiprocessors. The main idea is to implemen...
Ravi R. Iyer, Laxmi N. Bhuyan, Ashwini K. Nanda
ADBIS
2000
Springer
131views Database» more  ADBIS 2000»
15 years 11 months ago
Mobile Transaction Management in Mobisnap
Abstract. In this paper we describe a transaction management system designed to face the inherent characteristics of mobile environments. Mobile clients cache subsets of the databa...
Nuno M. Preguiça, Carlos Baquero, Francisco...
ARVLSI
1999
IEEE
162views VLSI» more  ARVLSI 1999»
15 years 11 months ago
Conjunction Search Using a 1-D, Analog VLSI-based, Attentional Search/Tracking Chip
The ability of animals to select a limited region of sensory space for scrutiny is an important factor in dealing with cluttered or complex sensory environments. Such an attention...
Timothy K. Horiuchi, Ernst Niebur