Sciweavers

5689 search results - page 709 / 1138
» A Performance Process Maturity Model
Sort
View
SIMPRA
2008
137views more  SIMPRA 2008»
15 years 6 months ago
An admissible-behaviour-based analysis of the deadlock in Petri-net controllers
This paper addresses the problem of verifying the discrete control logic that is typically implemented by programmable controllers. Not only are the logical properties of the cont...
G. Music, Drago Matko
CAL
2011
14 years 6 months ago
DRAMSim2: A Cycle Accurate Memory System Simulator
—In this paper we present DRAMSim2, a cycle accurate memory system simulator. The goal of DRAMSim2 is to be an accurate and publicly available DDR2/3 memory system model which ca...
Paul Rosenfeld, Elliott Cooper-Balis, Bruce Jacob
PLDI
2012
ACM
13 years 9 months ago
Adaptive input-aware compilation for graphics engines
While graphics processing units (GPUs) provide low-cost and efficient platforms for accelerating high performance computations, the tedious process of performance tuning required...
Mehrzad Samadi, Amir Hormati, Mojtaba Mehrara, Jan...
ICC
2008
IEEE
127views Communications» more  ICC 2008»
16 years 1 months ago
Delay Analysis of Distributed Reservation Protocol with UWB Shadowing Channel for WPAN
— Ultra-wideband (UWB) technology is expected to provide high data rate services for future wireless personal area networks (WPANs). The WiMedia Alliance recently has launched it...
Kuang-Hao Liu, Xuemin Shen, Ruonan Zhang, Lin Cai
ASPDAC
2009
ACM
139views Hardware» more  ASPDAC 2009»
16 years 1 months ago
Hardware-dependent software synthesis for many-core embedded systems
Abstract— This paper presents synthesis of Hardware Dependent Software (HdS) for multicore and many-core designs using Embedded System Environment (ESE). ESE is a tool set, devel...
Samar Abdi, Gunar Schirner, Ines Viskic, Hansu Cho...