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ICCAD
2005
IEEE
106views Hardware» more  ICCAD 2005»
15 years 12 months ago
Fast balanced stochastic truncation via a quadratic extension of the alternating direction implicit iteration
— Balanced truncation (BT) model order reduction (MOR) is known for its superior accuracy and computable error bounds. Balanced stochastic truncation (BST) is a particular BT pro...
Ngai Wong, Venkataramanan Balakrishnan
SIGGRAPH
2000
ACM
15 years 10 months ago
Pomegranate: a fully scalable graphics architecture
Pomegranate is a parallel hardware architecture for polygon rendering that provides scalable input bandwidth, triangle rate, pixel rate, texture memory and display bandwidth while...
Matthew Eldridge, Homan Igehy, Pat Hanrahan
FPL
2007
Springer
97views Hardware» more  FPL 2007»
15 years 10 months ago
An FPGA Approach to Quantifying Coherence Traffic Efficiency on Multiprocessor Systems
Recently, there is a surge of interests in using FPGAs for computer architecture research including applications from emulating and analyzing a new platform to accelerating microa...
Taeweon Suh, Shih-Lien Lu, Hsien-Hsin S. Lee
ATC
2008
Springer
15 years 8 months ago
Concepts for Autonomous Control Flow Checking for Embedded CPUs
In this paper, we introduce new concepts and methods for checking the correctness of control flow instructions during the execution of programs in embedded CPUs. Detecting and avoi...
Daniel Ziener, Jürgen Teich
AICCSA
2005
IEEE
129views Hardware» more  AICCSA 2005»
15 years 8 months ago
Enhanced visual evaluation of feature extractors for image mining
Plus BROWSE SEARCH IEEE XPLORE GUIDE SUPPORT View TOC Enhanced visual evaluation of feature extractors for image mining Rodrigues, J.F., Jr. Traina, A.J.M. Traina, C., Jr. Comput. ...
José Fernando Rodrigues Jr., Agma J. M. Tra...