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DATE
2009
IEEE
113views Hardware» more  DATE 2009»
16 years 1 months ago
Scalable compile-time scheduler for multi-core architectures
As the number of cores continues to grow in both digital signal and general purpose processors, tools which perform automatic scheduling from model-based designs are of increasing...
Maxime Pelcat, Pierrick Menuet, Slaheddine Aridhi,...
DSD
2003
IEEE
138views Hardware» more  DSD 2003»
15 years 11 months ago
A Two-step Genetic Algorithm for Mapping Task Graphs to a Network on Chip Architecture
Network on Chip (NoC) is a new paradigm for designing core based System on Chip which supports high degree of reusability and is scalable. In this paper we describe an efficient t...
Tang Lei, Shashi Kumar
ECBS
2002
IEEE
119views Hardware» more  ECBS 2002»
15 years 11 months ago
Managing Complex Temporal Requirements in Real-Time Control Systems
Design and implementation of motion control applications includes the transition from control design to real-time system implementation. To make this transition smooth, the specif...
Kristian Sandström, Christer Norström
ISLPED
2004
ACM
139views Hardware» more  ISLPED 2004»
15 years 11 months ago
Eliminating voltage emergencies via microarchitectural voltage control feedback and dynamic optimization
Microprocessor designers use techniques such as clock gating to reduce power dissipation. An unfortunate side-effect of these techniques is the processor current fluctuations th...
Kim M. Hazelwood, David Brooks
RECOMB
2010
Springer
15 years 4 months ago
Predicting Nucleosome Positioning Using Multiple Evidence Tracks
Abstract. We describe a probabilistic model, implemented as a dynamic Bayesian network, that can be used to predict nucleosome positioning along a chromosome based on one or more g...
Sheila M. Reynolds, Zhiping Weng, Jeff A. Bilmes, ...