130 search results - page 12 / 26 » A Novel Metric for Interconnect Architecture Performance |
165
click to vote
MICRO
2009
IEEE
16 years 21 days ago
2009
IEEE
Performance and power are the first order design metrics for Network-on-Chips (NoCs) that have become the de-facto standard in providing scalable communication backbones for mult...
147
click to vote
ISCA
2007
IEEE
16 years 10 days ago
2007
IEEE
We introduce a novel chip fabrication technique called “brick and mortar”, in which chips are made from small, pre-fabricated ASIC bricks and bonded in a designer-specified a...
137
click to vote
ARC
2009
Springer
15 years 10 months ago
2009
Springer
Abstract. This paper presents the very first implementation of a HyperTransport 3 physical layer interface for Field Programmable Gate Arrays. HyperTransport is a low latency, high...
160
click to vote
TMM
2002
15 years 5 months ago
2002
With the rapid performance improvements in low-cost PCs, it becomes increasingly practical and cost-effective to implement large-scale video-on-demand (VoD) systems around parallel...
161
click to vote
ISCC
2008
IEEE
16 years 13 days ago
2008
IEEE
The crossbar fabric is widely used as the interconnect of high-performance packet switches due to its low cost and scalability. There are two main variants of the crossbar fabric:...