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DAC
2007
ACM
16 years 7 months ago
Efficient Computation of Buffer Capacities for Cyclo-Static Dataflow Graphs
A key step in the design of cyclo-static real-time systems is the determination of buffer capacities. In our multi-processor system, we apply back-pressure, which means that tasks...
Maarten Wiggers, Marco Bekooij, Gerard J. M. Smit
DAC
2005
ACM
16 years 7 months ago
A lattice-based framework for the classification and design of asynchronous pipelines
This paper presents a unifying framework for the modeling of asynchronous pipeline circuits. A pipeline protocol is captured in a graph-based model which defines the partial order...
Peggy B. McGee, Steven M. Nowick
DAC
2006
ACM
16 years 7 months ago
Optimal simultaneous mapping and clustering for FPGA delay optimization
Both technology mapping and circuit clustering have a large impact on FPGA designs in terms of circuit performance, area, and power dissipation. Existing FPGA design flows carry o...
Joey Y. Lin, Deming Chen, Jason Cong
ISVLSI
2007
IEEE
139views VLSI» more  ISVLSI 2007»
16 years 27 days ago
Automatic Retargeting of Binary Utilities for Embedded Code Generation
Contemporary SoC design involves the proper selection of cores from a reference platform. Such selection implies the design exploration of alternative CPUs, which requires the gen...
Alexandro Baldassin, Paulo Centoducatte, Sandro Ri...
DAC
2009
ACM
16 years 7 months ago
WCET-aware register allocation based on graph coloring
Current compilers lack precise timing models guiding their built-in optimizations. Hence, compilers apply ad-hoc heuristics during optimization to improve code quality. One of the...
Heiko Falk