We present a new approach to the verification of hardware systems with data dependencies using temporal logic symbolic model checking. As a benchmark we take Tomasulo's algori...
Sergey Berezin, Armin Biere, Edmund M. Clarke, Yun...
Estimation of development effort without imposing overhead on the project and the development team is of paramount importance for any software company. This study proposes a new e...
Pekka Abrahamsson, Raimund Moser, Witold Pedrycz, ...
Don't-care conditions provide additional flexibility in logic synthesis and optimization. However, most work only focuses on the gate level because it is difficult to handle ...
For a number of years, dataflow concepts have provided designers of digital signal processing systems with environments capable of expressing high-level software architectures as ...
William Plishker, Nimish Sane, Shuvra S. Bhattacha...
A number of techniques and software tools for embedded system design have been recently proposed. However, the current practice in the designer community is heavily based on manua...
Alberto L. Sangiovanni-Vincentelli, Antonino Damia...