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ISCAS
2007
IEEE
128views Hardware» more  ISCAS 2007»
16 years 17 days ago
SAT-based ATPG for Path Delay Faults in Sequential Circuits
Due to the development of high speed circuits beyond the 2-GHz mark, the significance of automatic test pattern generation for Path Delay Faults (PDFs) drastically increased in t...
Stephan Eggersglüß, Görschwin Fey,...
SIGIR
2004
ACM
15 years 11 months ago
Dependence language model for information retrieval
This paper presents a new dependence language modeling approach to information retrieval. The approach extends the basic language modeling approach based on unigram by relaxing th...
Jianfeng Gao, Jian-Yun Nie, Guangyuan Wu, Guihong ...
ITC
2000
IEEE
91views Hardware» more  ITC 2000»
15 years 10 months ago
A mixed mode BIST scheme based on reseeding of folding counters
In this paper a new scheme for deterministic and mixed mode scan-based BIST is presented. It relies on a new type of test pattern generator which resembles a programmable Johnson ...
Sybille Hellebrand, Hans-Joachim Wunderlich, Huagu...
BMCBI
2005
142views more  BMCBI 2005»
15 years 6 months ago
CLU: A new algorithm for EST clustering
Background: The continuous flow of EST data remains one of the richest sources for discoveries in modern biology. The first step in EST data mining is usually associated with EST ...
Andrey A. Ptitsyn, Winston Hide
TCAD
1998
82views more  TCAD 1998»
15 years 6 months ago
LOT: Logic Optimization with Testability. New transformations for logic synthesis
—A new approach to optimize multilevel logic circuits is introduced. Given a multilevel circuit, the synthesis method optimizes its area while simultaneously enhancing its random...
Mitrajit Chatterjee, Dhiraj K. Pradhan, Wolfgang K...