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DATE
1999
IEEE
147views Hardware» more  DATE 1999»
15 years 11 months ago
Efficient BIST Hardware Insertion with Low Test Application Time for Synthesized Data Paths
In this paper, new and efficient BIST methodology and BIST hardware insertion algorithms are presented for RTL data paths obtained from high level synthesis. The methodology is ba...
Nicola Nicolici, Bashir M. Al-Hashimi
DEXAW
1999
IEEE
105views Database» more  DEXAW 1999»
15 years 11 months ago
Personalizing the Web Using Site Descriptions
The information overload on the Web has created a great need for efficient filtering mechanisms. Many sites (e.g., CNN and Quicken) address this problem by allowing a user to crea...
Vinod Anupam, Yuri Breitbart, Juliana Freire, Bhar...
IPPS
1999
IEEE
15 years 10 months ago
SCALA: A Framework for Performance Evaluation of Scalable Computing
Abstract. Conventional performance environments are based on pro ling and event instrumentation. It becomes problematic as parallel systems scale to hundreds of nodes and beyond. A...
Xian-He Sun, Mario Pantano, Thomas Fahringer, Zhao...
CONCUR
1999
Springer
15 years 10 months ago
Partial Order Reduction for Model Checking of Timed Automata
Abstract. The paper presents a partial order reduction method applicable to networks of timed automata. The advantage of the method is that it reduces both the number of explored c...
Marius Minea
MASS
2010
150views Communications» more  MASS 2010»
15 years 4 months ago
A non-replication multicasting scheme in delay tolerant networks
Delay tolerant networks (DTNs) are a special type of wireless mobile networks which may lack continuous network connectivity. Multicast is an important routing function that suppor...
Jie Wu, Yunsheng Wang