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FPL
2004
Springer
90views Hardware» more  FPL 2004»
15 years 12 months ago
Run-Time-Conscious Automatic Timing-Driven FPGA Layout Synthesis
Abstract. Layout tools for FPGAs can typically be run in two different modes: non-timing-driven and timing-driven. Non-timing-driven mode produces a solution quickly, without consi...
Jason Helge Anderson, Sudip Nag, Kamal Chaudhary, ...
ICRA
2003
IEEE
117views Robotics» more  ICRA 2003»
15 years 11 months ago
Map building with mobile robots in dynamic environments
The problem of generating maps with mobile robots has received considerable attention over the past years. Most of the techniques developed so far have been designed for situation...
Dirk Hähnel, Rudolph Triebel, Wolfram Burgard...
PLDI
2003
ACM
15 years 11 months ago
Taming the IXP network processor
We compile Nova, a new language designed for writing network processing applications, using a back end based on integer-linear programming (ILP) for register allocation, optimal b...
Lal George, Matthias Blume
IEEEPACT
2000
IEEE
15 years 11 months ago
Instruction Scheduling for Clustered VLIW DSPs
Recent digital signal processors (DSPs) show a homogeneous VLIW-like data path architecture, which allows C compilers to generate efficient code. However, still some special rest...
Rainer Leupers
PLDI
2005
ACM
16 years 2 days ago
Demystifying on-the-fly spill code
Modulo scheduling is an effective code generation technique that exploits the parallelism in program loops by overlapping iterations. One drawback of this optimization is that reg...
Alex Aletà, Josep M. Codina, Antonio Gonz&a...