We establish a new connection between the two most common traditions in the theory of real computation, the Blum-Shub-Smale model and the Computable Analysis approach. We then use...
Precise chip-level timing requires careful modeling of the interaction between logic drivers and interconnect. Existing static-timing analysis methodologies generate models for dr...
In this paper, we propose a new approach for VLSI interconnect global routing that can optimize both congestion and delay, which are often competing objectives. Our approach provi...
One important part of a HW/SW codesign system is the scheduler which is needed in order to determine if a given HW/SW partitioning is suitable for a given application. In this pap...
This paper introduces a new approach to adjust a class of neurofuzzy networks based on the idea of participatory learning. Participatory learning is a mean to learn and revise bel...
Michel Hell, Rosangela Ballini, Pyramo Costa Jr., ...