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» A Network on Chip Architecture and Design Methodology
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GLVLSI
2005
IEEE
124views VLSI» more  GLVLSI 2005»
15 years 11 months ago
SOFTENIT: a methodology for boosting the software content of system-on-chip designs
Embedded software is a preferred choice for implementing system functionality in modern System-on-Chip (SoC) designs, due to the high flexibility, and lower engineering costs pro...
Abhishek Mitra, Marcello Lajolo, Kanishka Lahiri
ASPDAC
2007
ACM
116views Hardware» more  ASPDAC 2007»
15 years 10 months ago
VLSI Design of Multi Standard Turbo Decoder for 3G and Beyond
Turbo decoding architectures have greater error correcting capability than any other known code. Due to their excellent performance turbo codes have been employed in several trans...
Imran Ahmed, Tughrul Arslan
VLSID
2010
IEEE
173views VLSI» more  VLSID 2010»
15 years 10 months ago
Voltage-Frequency Planning for Thermal-Aware, Low-Power Design of Regular 3-D NoCs
Network-on-Chip combined with Globally Asynchronous Locally Synchronous paradigm is a promising architecture for easy IP integration and utilization with multiple voltage levels. ...
Mohammad Arjomand, Hamid Sarbazi-Azad
DATE
2006
IEEE
100views Hardware» more  DATE 2006»
16 years 2 days ago
Simulation and analysis of network on chip architectures: ring, spidergon and 2D mesh
NoC architectures can be adopted to support general communications among multiple IPs over multi-processor Systems on Chip (SoCs). In this work we illustrate the modeling and simu...
Luciano Bononi, Nicola Concer
DSD
2003
IEEE
138views Hardware» more  DSD 2003»
15 years 11 months ago
A Two-step Genetic Algorithm for Mapping Task Graphs to a Network on Chip Architecture
Network on Chip (NoC) is a new paradigm for designing core based System on Chip which supports high degree of reusability and is scalable. In this paper we describe an efficient t...
Tang Lei, Shashi Kumar