497 search results - page 18 / 100 » A Network on Chip Architecture and Design Methodology |
165
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MTV
2003
IEEE
15 years 11 months ago
2003
IEEE
As embedded systems continue to face increasingly higher performance requirements, deeply pipelined processor architectures are being employed to meet desired system performance. ...
164
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ICCAD
2000
IEEE
15 years 10 months ago
2000
IEEE
Abstract— Deep submicron technology scaling has two major ramifications on the design process. First, reduced feature size significantly increases wire delay, thus resulting in...
165
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ISPD
1997
ACM
15 years 10 months ago
1997
ACM
- This paper reports on a highly effective methodology to construct complex high performance microprocessors. Critical aspects of the methodology include an integrated database for...
162
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GLVLSI
2005
IEEE
15 years 11 months ago
2005
IEEE
We have presented an optimal on-chip buffer allocation and buffer insertion methodology which uses stochastic models of the architecture. This methodology uses finite buffer s...
134
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DATE
2006
IEEE
16 years 2 days ago
2006
IEEE
Consumer electronics products, such as high-end (digital) TVs, contain complex systems on chip (SOC) that offer high computational performance at low cost. Traditionally, these SO...