497 search results - page 17 / 100 » A Network on Chip Architecture and Design Methodology |
153
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ISSS
2002
IEEE
15 years 11 months ago
2002
IEEE
We have fabricated a Chip Multiprocessor prototype code-named Merlot to proof our novel speculative multithreading architecture. On Merlot, multiple threads provide wider issue wi...
167
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DAC
1999
ACM
15 years 10 months ago
1999
ACM
As the family of Alpha microprocessors continues to scale into more advanced technologies with very high frequency edge rates and multiple layers of interconnect, the issue of cha...
156
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IEEEPACT
2006
IEEE
16 years 1 days ago
2006
IEEE
Previous studies have demonstrated the advantages of single-ISA heterogeneous multi-core architectures for power and performance. However, none of those studies examined how to de...
180
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COMPUTER
2002
15 years 5 months ago
2002
of abstraction and coarse granularity and distributed communication control. Focusing on using probabilistic metrics such as average values or variance to quantify design objective...
138
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DATE
2007
IEEE
16 years 10 days ago
2007
IEEE
In this paper we present a systematic comparison between two different implementations of a distributed Network on Chip: fully asynchronous and multi-synchronous. The NoC architec...