497 search results - page 15 / 100 » A Network on Chip Architecture and Design Methodology |
176
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DATE
2004
IEEE
15 years 9 months ago
2004
IEEE
Conventional physical design flow separates the design of power network and signal network. Such a separated approach results in slow design convergence for wire-limited deep sub-...
156
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CODES
2004
IEEE
15 years 9 months ago
2004
IEEE
In this paper, we present an approach for automatic synthesis of System on Chip (SoC) multiprocessor architectures for applications expressed as process networks. Our approach is ...
172
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VLSID
2008
IEEE
16 years 11 days ago
2008
IEEE
With the shift towards deep sub-micron (DSM) technologies, the increase in leakage power and the adoption of poweraware design methodologies have resulted in potentially significa...
197
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DAC
2010
ACM
15 years 6 months ago
2010
ACM
Given the increasing complexity of multi-processor systems-onchip, a wide range of parameters must be tuned to find the best trade-offs in terms of the selected system figures of ...
154
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DATE
2005
IEEE
15 years 8 months ago
2005
IEEE
In this paper, we provide a methodology to perform both bus partitioning and bus frequency assignment to each of the bus segment simultaneously while optimizing both power consump...